Hardware verification and debugging consume over 70% of digital Integrated Circuit (IC) design cycles. Hardware engineers spend thousands of hours manually parsing static timing reports, inspecting Value Change Dump (VCD) waveform traces in GTKWave, and writing SystemVerilog assertions (SVA). In this paper, we introduce EDA-Agent — an open-source, multi-agent artificial intelligence platform designed to automate Register-Transfer Level (RTL) code analysis, functional testbench generation, waveform failure debugging, synthesis area estimation, and timing slack optimization. EDA-Agent combines Large Language Models (LLMs) with deterministically bounded Abstract Syntax Tree (AST) static analysis, VCD waveform time-tick tracing, and Retrieval-Augmented Generation (RAG) over IEEE specifications. Our empirical evaluation demonstrates 100% unit test accuracy, 94.2% bug localization accuracy on VCD signal traces, a 37.5x acceleration in testbench generation compared to human engineers, and 89.5% functional coverage reachability.