Published on: August 2026
ON-CNN WITH INTEGRATED RELU ACTIVATION FOR FPGA-BASED CNN ACCELERATION
Samudrala Vandana Dr Dr Anvesh Thatikonda
2Associate Professor, Department Of ECE, SVS Group of Institutions, Hanmakonda, Telangana
Article Status
Available Documents
Abstract
Keywords: FPGA, Convolutional Neural Network (CNN), ON-CNN, ReLU Activation, Hardware Acceleration, Edge AI.
How to Cite this Paper
Vandana, S. & Thatikonda, D. D. A. (2026). ON-CNN with Integrated ReLU Activation for FPGA-Based CNN Acceleration. International Journal of Creative and Open Research in Engineering and Management, <i>02</i>(8), 1-14. https://doi.org/10.55041/ijcope.v2i8.256
Vandana, Samudrala, and Dr Thatikonda. "ON-CNN with Integrated ReLU Activation for FPGA-Based CNN Acceleration." International Journal of Creative and Open Research in Engineering and Management, vol. 02, no. 8, 2026, pp. 1-14. doi:https://doi.org/10.55041/ijcope.v2i8.256.
Vandana, Samudrala, and Dr Thatikonda. "ON-CNN with Integrated ReLU Activation for FPGA-Based CNN Acceleration." International Journal of Creative and Open Research in Engineering and Management 02, no. 8 (2026): 1-14. https://doi.org/https://doi.org/10.55041/ijcope.v2i8.256.
References
- Boutros, S. Nurvitadhi, C. de Prado, M. Blott, and K. Vissers, “FPGA-accelerated deep learning inference: Challenges and opportunities,” IEEE Micro, vol. 41, no. 5, pp. 46–54, 2021.
- Ma, H. Zhang, Y. Cao, J. Li, and Y. Chen, “Optimizing FPGA-based accelerator design for deep convolutional neural networks,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 3, pp. 573–586, 2021.
- Zhang, J. Wang, C. Zhu, Y. Lin, and Y. Wang, “Efficient FPGA implementation of convolutional neural networks using optimized dataflow architecture,” IEEE Access, vol. 9, pp. 112034–112046, 2021.
- Alwani, H. Chen, M. Ferdman, and P. Milder, “Fused-layer CNN accelerators for FPGA platforms,” Integration, the VLSI Journal, vol. 81, pp. 34–46, 2021.
- Qiu, J. Wang, S. Yao, K. Guo, B. Li, and Y. Wang, “Deep learning acceleration with FPGA-based convolution engines,” Microprocessors and Microsystems, vol. 82, Art. no. 103909, 2021.
- Mittal, “A survey of FPGA-based accelerators for convolutional neural networks,” Journal of Systems Architecture, vol. 117, Art. no. 102149, 2021.
- Liu, H. Fan, and Y. Chen, “Resource-efficient FPGA architecture for real-time CNN inference,” Electronics, vol. 10, no. 18, pp. 1–18, 2021.
- Wang, Y. Li, and X. Huang, “High-throughput FPGA accelerator for convolutional neural networks using parallel processing elements,” IEEE Access, vol. 10, pp. 35812–35824, 2022.
- N. Whatmough, S. K. Lee, H. Zhou, and M. Mattina, “Energy-efficient FPGA implementations for deep neural network inference,” IEEE Transactions on Computers, vol. 71, no. 4, pp. 1018–1031, 2022.
- M. Rahman, M. A. Islam, and S. Hossain, “Low-latency FPGA architecture for CNN-based image classification,” AEU – International Journal of Electronics and Communications, vol. 148, Art. no. 154151, 2022.
- Li, T. Wang, and Y. Zhang, “Hardware-efficient ReLU implementation for FPGA-based deep learning accelerators,” Microelectronics Journal, vol. 125, Art. no. 105482, 2022.
- Chen, X. Liu, and H. Wu, “Integrated convolution and activation architecture for FPGA-based CNN acceleration,” Journal of Signal Processing Systems, vol. 94, no. 9, pp. 1121–1134, 2022.
- Kumar and A. Singh, “Parallel CNN accelerator design using FPGA for edge intelligence applications,” International Journal of Reconfigurable Computing, vol. 2022, pp. 1–12, 2022.
- Li, Q. Wang, and Z. Chen, “FPGA-based edge AI accelerator with optimized convolution and activation layers,” Electronics, vol. 11, no. 14, pp. 1–20, 2022.
- Roy, P. Banerjee, and A. Bhattacharya, “Performance analysis of FPGA-implemented convolutional neural networks for embedded vision systems,” Microprocessors and Microsystems, vol. 94, Art. no. 104641, 2023.
- Zhao, J. Sun, and Y. Liu, “Memory-efficient CNN accelerator architecture for FPGA-based inference systems,” IEEE Access, vol. 11, pp. 48216–48230, 2023.
- Gupta and R. Verma, “High-performance FPGA implementation of deep learning inference engines using pipelined convolution architectures,” Journal of Systems Architecture, vol. 141, Art. no. 102915, 2023.
- S. Rao, V. Prakash, and S. Kumar, “Resource-aware CNN accelerator with integrated activation processing for FPGA devices,” AEU – International Journal of Electronics and Communications, vol. 167, Art. no. 154758, 2023.
- Zhang, H. Yang, and L. Wang, “Low-power FPGA accelerator for real-time convolutional neural network inference,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 33, no. 8, pp. 4128–4140, 2023.
- Zhou, C. Li, and M. Huang, “Scalable FPGA architecture for CNN acceleration in edge computing environments,” IEEE Access, vol. 12, pp. 12451–12466, 2024.
Ethical Compliance & Review Process
- •All submissions are screened under plagiarism detection.
- •Review follows editorial policy.
- •Authors retain copyright.
- •Peer Review Type: Double-Blind Peer Review
- •Published on: Aug 27 2026
This article is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License. You are free to share and adapt this work for non-commercial purposes with proper attribution.

