Finite Impulse Response (FIR) filters are required in the digital signal processing systems like communication systems and analysis of signals. Traditional multiplier-based realizations create a high level of complexity in the hardware and Distributed Arithmetic (DA) lowers the count of multipliers at the cost of a memory overhead. New architectures like Reconfigurable Partial Product Generator (RRPG) based FIR filters are more efficient in the use of hardware because they use fewer resources. The FIR filter is implemented as the RRPG based baseline architecture in this work and it is subsequently improved with Least Mean Square (LMS) adaptive algorithm. The LMS algorithm compares the desired and actual output and updates filter coefficients in an iterative manner to minimize the error between them thus further enhancing filtering accuracy. The suggested RRPG+LMS architecture is tested using MATLAB simulation and implemented in Verilog HDL with Xilinx Vivado. The experimental findings have shown that when the LMS is integrated, the mean square error is greatly minimized compared to the RRPG-based FIR filter operating alone whereas maintaining efficient hardware performance. The fact that the results of the MATLAB and the hardware are close to each other proves the accuracy and usefulness of the given approach to real-time FPGA-based systems.

Keywords: FIR Filter, RRPG, LMS Algorithm, FPGA, Adaptive Filtering, Error Reduction.